1. Field of the Invention
The present invention relates to a fabrication method of a semiconductor device and more particularly, to a fabrication method of a semiconductor device with the Complementary Metal-Oxide-Semiconductor (CMOS) structure, in which silicide layers of a refractory metal are formed in self-alignment in the surface areas of gate electrodes and source/drain regions of n- and p-channel MOS Field-Effect Transistors (MOSFETs).
2. Description of the Prior Art
A conventional fabrication method of a semiconductor device of this sort is shown in FIGS. 1A to 1C, which is disclosed in the Japanese Non-Examined Patent Publication No. 8-78361 published in 1996.
This method employs the known Self-Aligned siLICIDE (SALICIDE) process and provides refractory-metal silicide layers with low electric resistance while preventing the short circuit between wiring lines.
In this method, amorphous silicon layers or regions are formed in the surface areas of impurity-doped silicon regions of a single-crystal silicon (Si) substrate. Next, a refractory metal such as titanium (Ti) is deposited on the amorphous silicon layers or regions while heating the substrate to a temperature at which no silicide of the deposited refractory metal is generated. Finally, the substrate is subjected to a heat treatment for silicidation reaction so that the amorphous silicon layers react with the deposited refractory metal to thereby form silicide layers of the deposited refractory metal.
First, as shown in FIG. 1A, a field oxide layer 104 with a thickness of 200 to 400 nm is selectively formed in the surface area of a p-type single-crystal silicon substrate 101 by the selective oxidation technique, thereby defining an NMOS region 121 where an n-channel MOSFET is formed and a PMOS region 122 where a p-channel MOSFET in the surface area of the substrate 101.
Next, a p-type well region 102 and an n-type well region 103 are formed in the NMOS and PMOS regions 121 and 122 by the ion-implantation technique, respectively.
Then, gate oxide layers 105 with a thickness of 3 to 6 nm are formed on the exposed surfaces of the NMOS and PMOS regions 121 and 122 by the thermal oxidation technique. Subsequently, polysilicon gate electrodes 106 with a thickness of 150 to 250 nm are formed on the gate oxide layers 105 in the NMOS and PMOS regions 121 and 122 by the Chemical Vapor Deposition (CVD), photolithography, and etching techniques.
Pairs of oxide sidewalls 107 with a width of 80 to 150 nm are then formed on the gate oxide layers 105 at each side of the corresponding gate electrodes 106 in the NMOS and PMOS regions 121 and 122 by using the CVD and anisotropic etching techniques.
An oxide layer 108 with a thickness of 5 to 10 nm is formed to entirely cover the NMOS and PMOS regions 121 and 122 by the CVD technique.
Further, a pair of n-type source/drain regions 109 and a pair of p-type source/drain regions 110 are formed in the NMOS and PMOS regions 121 and 122 through the oxide layer 108 by the ion-implantation technique and the annealing technique, respectively.
When the pair of n-type source/drain regions 109 are formed in the NMOS region 121, arsenic (As) ions as an n-type dopant are selectively implanted into the NMOS region 121 with a dose of 2 to 5.times.10.sup.15 atoms/cm.sup.2 at an acceleration energy of 20 to 50 keV while the PMOS region 122 is covered with a patterned photoresist film (not shown). When the pair of p-type source/drain regions 110 are formed in the PMOS region 122, boron difluoride (BF.sub.2) ions as a p-type dopant are selectively implanted into the PMOS region 122 with a dose of 2 to 5.times.10.sup.15 atoms/cm.sup.2 at an acceleration energy of 20 to 50 keV while the NMOS region 121 is covered with a patterned photoresist film (not shown).
The pair of n-type source/drain regions 109 and the pair of p-type source/drain regions 110 thus formed are then subjected to an annealing process for activating the implanted arsenic and boron atoms. This annealing process is typically carried out at a temperature of 1000 to 1050.degree. C. for 10 to 30 seconds.
The state at this stage is shown in FIG. 1A.
Following the annealing process, as shown in FIG. 1B, arsenic ions are implanted again into the pairs of the n- and p-type source/drain regions 109 and 110 and the gate electrodes 106 in the NMOS and PMOS regions 121 and 122 through the oxide layer 108, as indicated by vertical arrows 115. Thus, amorphous silicon regions 106a are formed by the surface areas of the gate electrodes 106 in the NMOS and PMOS regions 121 and 122 and at the same time, amorphous silicon regions 109a and 110a are formed by the surface areas of the pairs of n- and p-type source/drain regions 109 and 110 in the NMOS and PMOS regions 121 and 122, respectively.
The reason because arsenic is selected for the ion-implantation species in this process is that arsenic has a largest mass number within the popularly-used n-type dopants in the semiconductor device fabrication and therefore, arsenic is optimum for this purpose.
Further, the oxide layer 108 is removed to expose the amorphous silicon regions 106a of the gate electrodes 106 and the amorphous silicon regions 109a and 110a of the pairs of source/drain regions 109 and 110 from the oxide layer 108. Then, a titanium (Ti) layer (not shown) with a thickness of 20 to 40 nm is deposited to cover the entire surface of the substrate 101 by the sputtering technique. The titanium layer is contacted with the exposed amorphous silicon regions 106a of the gate electrodes 106 and the exposed amorphous silicon regions 109a and 110a of the pairs of source/drain regions 109 and 110.
The titanium layer and the entire substrate 101 are subjected to a heat treatment at a temperature of 650 to 750.degree. C. for 10 to 30 seconds, thereby reacting the titanium layer with the amorphous silicon regions 106a of the gate electrodes 106 and the amorphous silicon regions 109a and 110a of the pairs of source/drain regions 109 and 110. Through this heat treatment, the titanium silicide (TiSi.sub.2) layers 111 with a thickness of 30 to 60 nm are formed in self-alignment to the gate electrodes 106 and the pairs of source/drain regions 109 and 110 due to silicidation reaction, respectively.
The unreacted titanium layer is then removed. The state at this stage is shown in FIG. 1C.
Finally, the titanium silicide layers 111 are subjected to a heat-treatment at a temperature of 800 to 900.degree. C. for 10 to 30 seconds, thereby causing the phase transition in the layers 111 to decrease their electric resistivity.
With the conventional fabrication method of a semiconductor device shown in FIGS. 1A to 1C, however, the following problem will occur.
There is a tendency that the silicidation reaction of titanium (Ti) with silicon (Si) into which arsenic (As) ions have been implanted with the dose of 2 to 5.times.10.sup.15 atoms/cm.sup.2 is more difficult to progress than the case where boron difluoride (BF.sub.2) ions are implanted thereinto instead of arsenic. Therefore, when the acceleration energy of arsenic ions is low, the thickness of the titanium silicide layers 111 in the NMOS region 121 becomes small compared with the titanium silicide layers 111 in the PMOS region 122.
In this case, the titanium silicide layers 111 in the NMOS region 121 tend to have an unsatisfactory small thickness, even if the titanium silicide layers 111 in the PMOS region 122 have a satisfactory large thickness. As a result, agglomeration of titanium silicide tends to occur in the titanium silicide layers 111 during the subsequent heat-treatment process for activating the implanted arsenic atoms, thereby increasing conspicuously the sheet resistance of the titanium silicide layers 111 in the NMOS region 121.
To avoid such the sheet resistance increase of the titanium silicide layers 111 in the NMOS region 121 as described above, it is popular that the acceleration energy of arsenic ions is set as high as possible to thereby increase the resultant thickness of the amorphous silicon regions 106a, 109a, and 110a in the NMOS and PMOS regions 121 and 122. The increased thickness of the amorphous silicon regions 106a, 109a, and 110a accelerates the silicidation reaction of titanium with arsenic-implanted amorphous silicon and consequently, the above problem of the sheet resistance increase of the titanium silicide layers 111 in the NMOS region 121 can be prevented from occurring.
However, the increased thickness of the amorphous silicon regions 106a and 110a in the PMOS region 122 will cause another problem that the junction leakage current of the pair of p-type source/drain regions 110 in the PMOS region 122 becomes high.
The inventor found that this problem is due to the following reason.
FIG. 2 schematically shows the profile of the dopant concentration of the pairs of p-type source/drain regions 110 in the PMOS region 122 as a function of depth.
In FIG. 2, the curve A indicates the dopant concentration distribution due to the boron-difluoride-ion implantation for forming the pair of p-type source/drain regions 110. The straight line B indicates the dopant concentration distribution of the n-type well region 103. The curve C indicates the dopant concentration distribution due to the arsenic-ion implantation for forming the amorphous silicon regions 110a in the pair of p-type source/drain regions 110. The curve D indicates the resultant or overall dopant concentration distribution of the pair of p-type source/drain regions 110 after the arsenic-ion implantation for forming the amorphous silicon regions 110a.
As seen from FIG. 2, the depth X.sub.j0 of the p-n junctions of the pair of p-type source/drain regions 110 before the arsenic-ion implantation for forming the amorphous silicon regions 110a is given by the intersection of the curve A and the straight line B. On the other hand, the depth X.sub.j1 of the p-n junctions of the pair of p-type source/drain regions 110 after the arsenic-ion implantation for forming the amorphous silicon regions 110a is given by the intersection of the curve D and the straight line B.
It is clear that the depth X.sub.j1 is smaller than the depth X.sub.j0. This is caused by the fact that the p-type dopant (i.e., BF.sub.2) doped into the pair of p-type source/drain regions 110 is canceled or eliminated by the n-type dopant (i.e., As) at the tail or bottom of the distribution of the implanted p-type dopant (i.e., BF.sub.2), i.e., in the vicinity of the p-n junctions of the p-type source/drain regions 110. As a result, the tail or bottom of the distribution of the implanted p-type dopant is raised toward the surfaces of the regions 110. In other words, the p-n junctions of the pair of p-type source/drain regions 110 become shallow. These shallow p-n junctions increase the junction leakage current of the pair of p-type source/drain regions 110 in the PMOS region 122 due to spikes or crystal defects.
Concretely, to fabricate a p- or n-channel MOSFET having a gate length of approximately 0.15 .mu.m, the depth of the p-n junctions of a pair of source/drain regions with respect to their surfaces needs to be set as approximately 0.15 .mu.m or less from the viewpoint of suppression of the short channel effect.
On the other hand, to set the sheet resistance of a titanium silicide layer in a gate electrode of an n-channel MOSFET at 10 .OMEGA./.quadrature. or less, the acceleration energy of an n-type dopant (i.e., As ions) for forming an amorphous region in the gate electrode needs to be set as 60 keV or higher. However, if arsenic ions are implanted at an acceleration energy of 60 keV or higher with a dose of 2 to 5.times.10.sup.14 atoms/cm.sup.2, the tail or bottom of the implanted arsenic ions will have a depth of 0.1 .mu.m or larger.
Thus, the bottom or tail of the distribution of the implanted p-type dopant (i.e., BF.sub.2 ions) for forming the p-type source/drain regions 110 is canceled by the implanted n-type dopant (i.e., As ions) for forming the amorphous region, thereby decreasing the depth of the p-n junctions of the pair of p-type source/drain regions 110.